1. Field of the Invention
The present invention relates to a DC (Direct Current) voltage generation circuit and a pulse generation circuit thereof, especially to a DC voltage generation circuit and a pulse generation circuit thereof that prevent short current from occurring.
2. Description of Related Art
Please refer to FIG. 1, illustrating a circuit of a conventional switching regulator. The switching regulator 100 comprises a PMOS 110 and an NMOS 120, connecting in series between a DC voltage level Vcc and ground. The PMOS 110 has its source coupled to the DC voltage level Vcc and its drain coupled to the node LX, and the NMOS 120 has its source coupled to ground and its drain coupled to the node LX. The on/off state of the PMOS 110 is controlled by the gate control signal PG. When the gate control signal PG is at low level the PMOS 110 is on, and when the gate control signal PG is at high level the PMOS 110 is off. The on/off state of the NMOS 120 is controlled by the gate control signal NG. When the gate control signal NG is at high level the NMOS 120 is on, and when the gate control signal NG is at low level the NMOS 120 is off. The gate control signal PG and the gate control signal NG become a delay signal PD and a delay signal ND after passing through a delay unit 142 and a delay unit 132 respectively. The delay signal ND is inverted by a NOT gate 134 before being input to a NAND gate 136, which receives a control signal CTRL at its other terminal and outputs the gate control signal PG at its output terminal; similarly, the delay signal PD is inverted by a NOT gate 144 before being input to a NOR gate 146, which receives the control signal CTRL at its other terminal and outputs the gate control signal NG at its output terminal.
Please refer to FIG. 2, illustrating a timing diagram of the control signals and the delay signals of the conventional switching regulator 100. When the control signal CTRL transits from low level to high level (in order to turn on the PMOS 110), the gate control signal NG transits immediately from high level to low level, which immediately turns off the NMOS 120 to prevent the PMOS 110 and the NMOS 120 from turning on at the same time. After a delay time Td, the delay signal ND transits from high level to low level. As the inversion of the delay signal ND and the control signal CTRL both are at high level at the time, the gate control signal PG outputted by the NAND gate 136 transits to low level; namely, the PMOS 110 turns on at a delay time Td after the NMOS 120 turns off. After another delay time Td, the delay signal PD transits from high level to low level, reflecting the on state of the PMOS 110. After an enabling time Ton the control signal CTRL transits from high level to low level (in order to turn on the NMOS 120), which in turn makes the gate control signal PG transit immediately from low level to high level to turn off the PMOS 110 immediately so that the PMOS 110 and the NMOS 120 do not turn on at the same time. After the delay time Td, the delay signal PD transits from low level to high level. As the inversion of the delay signal PD and the control signal CTRL both are at low level at the time, the gate control signal NG outputted by the NOR gate 146 transits to high level; namely, the NMOS 120 turns on at the delay time Td after the PMOS 110 turns off. After another same delay time Td, the delay signal ND transits from low level to high level, reflecting the on state of the NMOS 120. As a result, continuous pulse signals are generated at the node LX by adjusting the duty cycle of the control signal CTRL. After the pulse signals pass through a low-pass filter 150, which is comprised of an inductor 152 and a capacitor 154, a DC voltage is generated at the output terminal OUT.
The feature of the circuit shown in FIG. 1 is that the gate control signal PG and the gate control signal NG are fed back to the NMOS 120 and the PMOS 110 respectively after a delay time so that when the gate control signal PG is at low level the gate control signal NG is not at high level, avoiding a short current caused by simultaneous turning on of both the PMOS 110 and the NMOS 120. Therefore, this kind of circuit is referred to as a feedback delay control circuit. This circuit, however, has a main drawback that when the enabling time Ton of the control signal CTRL is greater than the delay time Td but less than twice the delay time Td, (i.e., Td<Ton<2Td), there is a possibility that the PMOS 110 and the NMOS 120 turns on at the same time, resulting in the occurrence of the shout current. Please refer to FIG. 3, illustrating another timing diagram of the control signals and the delay signals of the conventional switching regulator 100. When the gate control signal PG transits from high level to low level to turn on the PMOS 110, the delay signal PD will not reflect the on state of the PMOS 110 until a delay time Td has elapsed. If, within the delay time Td, the control signal CTRL transits from high level to low level (in order to turn on the NMOS 120), despite the gate control signal PG transits immediately from low level to high level to turn off the PMOS 110 immediately, the gate control signal NG transits immediately from low level to high level since the delay signal PD is still at high level at the time, resulting in a simultaneous transition of both the gate control signal PG and the gate control signal NG, as depicted by the dotted circle in FIG. 3. As a result, because of inherent circuit delay of the components, a short current that damages the circuit components may probably occur during the transition time of both the gate control signal PG and the gate control signal NG when the PMOS 110 and the NMOS 120 turn on at the same time. In short, a short current will occur if the enabling time Ton or the non-enabling time of the control signal CTRL is less than twice the delay time Td.